The present invention relates generally to integrated circuits, and more particularly to memory sensing circuits having low latency or delay.
Memory devices are integral to a computer system and to many electronic circuits. Continuous improvements in the operating speed and computing power of a central processing unit (CPU) enable operation of an ever-greater variety of applications, many of which require faster and larger memories. Larger memories can be obtained by shrinking the geometry of the memory cells and the data/control lines within the memory devices. Faster operating speed can be obtained by reducing the charge and discharge times of parasitic capacitance on internal data lines and by improving the data-clocking scheme within the memory devices.
Conventionally, a memory access to retrieve a data bit is performed by: (1) activating a row control line (e.g., a row select line or a word line) for the data bit; (2) waiting for the charge that is stored in a memory cell corresponding to the data bit to generate a voltage on a sense line; (3) sensing the charged voltage on the sense line to determine the value of the data bit; (4) activating a column select line; (5) providing the detected bit value to a data line; and (6) buffering and providing the data bit to an input/output (I/O) pin of the memory device. Conventionally, these steps are performed in sequential order for an accessed data bit. These steps define the access time of the memory device (i.e., to read a data bit), which in turn determines the data transfer rate.
For a dynamic random access memory (DRAM), a memory cell is typically implemented with a small capacitor coupled to a switch. When the memory cell is selected (by activating the switch) the capacitor is coupled to the sense line and shares charge with the parasitic capacitor on the sense line. Since the memory cell capacitance is typically much smaller than the parasitic capacitance, the voltage on the sense line only moves a small amount as a result of the charge sharing. One or more amplifiers are then used to amplify and buffer the voltage on the sense line to allow for accurate detection of the voltage, and thus the value stored in the memory cell. After sensing is completed, the amplifiers are also used to recharge the capacitor to it proper logic state (i.e., its previous state before the read cycle).
For a densely integrated memory device, a large number of memory cells are implemented on one device and many memory cells are coupled to each sense line. As a result, the memory cell capacitor is typically small and the parasitic capacitance on the sense line can be large (relatively). These characteristics result in a longer charge time for the sense line, which can correspond to a longer memory read cycle and a slower data access rate.
As can be seen, circuits that can improve the charge time of the sense line and the detection of the voltage on the sense line are highly desirable.